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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8018 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 5 v, rail-to-rail, high-output current, xdsl line drive amplifier features ideal xdsl line drive amplifier for usb, pcmcia, or pci-based customer premise equipment (cpe). the ad8018 provides maximum reach on 5 v supply, driving 16 dbm of power into a back-terminated, transformer-coupled 100 while maintaining C82 dbc of out-of-band sfdr. rail-to-rail output voltage and high output current drive 400 ma output current into differential load of 10 @ 8 v p-p low single-tone distortion C86 dbc worst harmonic, 6 v p-p into d ifferential 10 @ 100 khz low noise 4.5 nv/ hz voltage noise density, 100 khz out-of-band sfdr = C82 dbc, 144 khz to 500 khz, r load = 12.5 , p line = 13 dbm low-power operation 3.3 v to 8 v power supply range two logic bits for standby and shutdown low supply current of 9 ma/amplifier (typ) current feedback amplifiers high speed 130 mhz bandwidth (C3 db) 300 v/ s slew rate applications xdsl usb, pci, pcmcia cards consumer dsl modems twisted pair line driver product description the ad8018 is intended for use in single-supply (5 v) xdsl modems where high-output current and low distortion are essential to achieve maximum reach. the dual high-speed amplifiers are capable of driving low distortion signals to within 0.5 v of the power supply rail. each amplifier can drive 400 ma of current into 10 ? (differential) while maintaining C82 dbc out-of-band sfdr. the ad8018 is available with flexible standby and shutdown modes. two digital logic bits (pwdn1 and pwdn0) may be used to put the ad8018 into one of three modes: full power, standby (outputs low impedance), and shutdown (outputs high impedance). fabricated with adis high-speed xfcb (extra fast comple- mentary bipolar) process, the high bandwidth and fast slew rate of the ad8018 keep distortion to a minimum, while dissipat- ing a minimum of power. the quiesc ent current of the ad8018 is a low 9 ma/amplifier. the ad8018 drive capability comes in compact 8-lead th ermal coastline s oic and 14-lead tssop packages. low-distor tion, rail-to-rail output voltage, and high- current drive in small packages make the ad8018 ideal for use in low-cost usb, pcmcia, and pci customer premise equipment for adsl, sdsl, vdsl, and proprietary xdsl systems. both models will operate over the temperature range C40 c to +85 c. 10 1nf 5v 750 v in 10 1nf 750 750 0.01 f 0.01 f v ref 0.01 f 100 100 10k 10k p out 16dbm r1 3.1 r2 3.1 r l = 100 line- power 13dbm transformer 1:4 10k 10k figure 2. single-supply voltage differential drive circuit for xdsl applications 8-lead soic (thermal coastline) v s ?n2 in2 6 5 7 8 out2 out1 ?n1 in1 ? s 1 2 3 4 ad8018ar pin configurations 14-lead tssop out1 in1 in1 v s pwdn1 v s out2 in2 in2 pwdn0 dgnd ad8018aru 6 5 7 8 1 2 3 4 9 14 13 12 11 10 nc nc nc nc = no connect p line dbm sfdr dbc 70 80 90 60 50 40 30 418 6 8 10 12 14 16 n = 4.0 v s = 3.3v v s = 5v v s = 8v figure 1. out-of-band sfdr vs. adsl upstream line power; v s = 5 v, n = 4 turns, 144 khz to 500 khz. see evaluation board schematics in figure 11.
rev. a C2C ad8018?pecifications (@ 25 c, v s = 5 v, r l = 100 , r f = r g = 750 unless otherwise noted.) parameter conditions min typ max unit dynamic performance C3 db bandwidth g = 1, v out < 0.4 v p-p, r l = 5 ? 40 50 mhz g = 1, v out < 0.4 v p-p, r l = 100 ? 100 130 mhz g = 2, v out < 0.4 v p-p, r l = 5 ? 35 40 mhz g = 2, v out < 0.4 v p-p, r l = 100 ? 80 100 mhz 0.1 db bandwidth v out < 0.4 v p-p, r l = 100 ? 10 mhz large signal bandwidth v out = 4 v p-p, g = +2 80 mhz slew rate noninverting, v out = 4 v p-p 300 v/ s rise and fall time noninverting, v out = 2 v p-p 5.5 ns settling time 0.1%, v out = 2 v p-p, r l = 100 ? 25 ns noise/harmonic performance distortion, v out = 6 v p-p (differential) second harmonic 100 khz, r l = 10 ? C89 C94 dbc 500 khz, r l = 10 ? C61 C63 dbc third harmonic 100 khz, r l = 10 ? C86 C89 dbc 500 khz, r l = 10 ? C74 C77 dbc mtpr (in-band) 25 khz to 138 khz, r l = 12.5 ? , p line = +13 dbm C70 dbc sfdr (out-of-band) 144 khz to 500 khz, r l = 12.5 ? , p line = +13 dbm C82 dbc input noise voltage f = 100 khz 4.5 5 nv hz input noise current f = 100 khz (+inputs) 1 pa hz f = 100 khz (Cinputs) 10 pa hz crosstalk f = 1 mhz, g = +2 C74 db dc performance input offset voltage 115mv t min to t max 17 mv input offset voltage match 0.1 2.6 mv transimpedance v out = 2 v p-p, r l = 5 ? 830 2000 k ? t min to t max 700 k ? input characteristics input resistance +input 10 m Cinput 125 ? input capacitance +input 1 pf input bias current (C) 0.3 8 a t min to t max 14 a input bias current (C) match 0.1 5.5 a t min to t max 8 a input bias current (+) 1 1.5 a t min to t max 2.5 a input bias current (+) match 0.1 0.5 a t min to t max 1 a cmrr v in 2 v to 4 v 51 54 db input cm voltage range 1.2 3.8 v output characteristics cap load 30% overshoot 1000 pf output resistance frequency = 100 khz, pwdn1, pwdn0 = 1 0.2 ? output voltage swing r l = 100 ? 0.16 to 4.87 v r l = 5 ? 0.5 to 4.5 v linear output current sfdr < C85 dbc, f = 100 khz, r l = 10 ? , differential 350 400 ma short-circuit current 1000 ma power supply supply current/amp pwdn1 = 1, pwdn0 = 1 9 10 ma t min to t max 11.4 ma stby supply current/amp pwdn1 = 0, pwdn0 = 1 or 4.5 5.1 ma pwdn1 = 1, pwdn0 = 0 4.5 5.1 ma shutdown supply current/amp pwdn1 = 0, pwdn0 = 0 0.3 0.55 ma operating range single supply 3.3 8 v +power supply rejection ratio v s = 1 v 60 66 db t min to t max 56 db Cpower supply rejection ratio v s = 1 v 52 55 db t min to t max 50 db
rev. a C3C ad8018 parameter conditions min typ max unit logic inputs (pwdn1, 0) logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic input bias current 240 a standby recovery time r l = 10 ? , g = +2, i s = 90% of typical 500 ns speci?cations subject to change without notice. ordering guide temperature package package model range description option ad8018ar C40 c to +85 c 8-lead plastic so-8 soic ad8018arCreel C40 c to +85 c 8-lead soic so-8 ad8018arCreel7 C40 c to +85 c 8-lead soic so-8 ad8018aru C40 c to +85 c 14-lead plastic ru-14 tssop ad8018aruCreel C40 c to +85 c 14-lead plastic ru-14 tssop ad8018aruCreel7 C40 c to +85 c 14-lead plastic ru-14 tssop ad8018aruCeval evaluatio n board ru-14 absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v internal power dissipation 2 small outline package (r) . . . . . . . . . . . . . . . . . . . 650 mw tssop package (ru) . . . . . . . . . . . . . . . . . . . . . . 565 mw input voltage (common-mode) . . . . . . . . . . . . . . . . . . . . v s logic voltage, pwdn0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 1.6 v output short circuit duration . . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range ru, r . . . . . . . C65 c to +150 c operating temperature range . . . . . . . . . . . C40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for the device on a 4-layer board in free air at 85 c: 8-lead soic package: ja = 100 c/w. 14-lead tssop package: ja = 115 c/w. maximum power dissipation the maximum power that can be safely dissipated by the ad8018 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. while the ad8018 is internally short circuit protected, this may not be suf?cient to guarantee that the maximum junction tempera- ture (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves. ambient temperature c 2.0 50 maximum power dissipation watts 1.5 1.0 0.5 0 40 30 20 100 10 2030 4050 6070 8090 t j = 150 c 14-lead tssop package 8-lead soic package figure 3. plot of maximum power dissipation vs. temperature caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8018 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a ad8018 C4C ad8018 v s v signal 50 750 750 v s r load v out 10 f tant 10 f tant 0.1 f 0.1 f tpc 1. single-ended test circuit time ns 0 output voltage mv 50 100 150 50 100 0 50 100 150 g = 2 v s = 2.5v r l = 5 150 200 250 300 350 400 450 500 tpc 2. small signal step response time ns 0 output voltage v 1 2 3 50 100 0 1 2 3 g = 2 v s = 2.5v r l = 5 150 200 250 300 350 400 450 500 tpc 3. large signal step response typical performance characteristics 1 frequency hz 10 10 1 100 1000 100 1k 10k 100k 1m 0.1 10 100 v s = 2.5v r l = 100 v noise i noise i noise v noise nv/ hz (rti) i noise pa/ hz tpc 4. i noise and v noise vs. frequency frequency mhz 0.01 output impedance 500 0 2k 2.5k 3k (1,1) (0,0) 1.5k 1k 0.1 1 10 100 1k (1,0) v s = 2.5v tpc 5. output impedance vs. frequency, for full power, standby, and shutdown modes mv 1 2 3 1 2 3 0 g = 2 v s = 2.5 v in = 2v p-p r l = 100 0 10 20 30 40 50 60 70 80 100 90 time ns v out (v in 2) ( 0.1%) (+0.1%) tpc 6. 0.1% settling time
rev. a ad8018 C5C frequency hz 10k output voltage dbv 25 1m 5 10m 100m 1g 100k 22 19 16 13 10 7 4 1 2 g = 2 v s = 2.5v r l = 100 tpc 7. output voltage vs. frequency load resistance 1 output swing volts 1.9 1.7 1.5 10 2.1 2.5 100 1000 10k 1.6 1.8 2.0 2.2 2.3 2.4 swing swing v s = 2.5v tpc 8. output swing vs. r load frequency hz 100k psrr db 70 90 1m 10m 100m 80 60 50 40 30 20 10 0 g = 2 v s = 2.5v v s = 1v r l = 100 psrr psrr tpc 9. psrr vs. frequency frequency hz 10k output voltage dbv 25 1m 5 10m 100m 1g 100k 22 19 16 13 10 7 4 1 2 g = 2 v s = 2.5v r l = 5 1,%(4 ) !
8 frequency hz 100k normalized gain db 6 1m 0 4 10m 100m 1g 5 4 3 2 1 1 2 3 (1,1) (1,0) or (0,1) g = 2 v s = 2.5v r l = 100 full power standby r l v out v in 50 750 750 tpc 11. small signal frequency response frequency hz 100k cmrr db 70 1m 10m 100m 60 50 40 30 20 10 1g g = 2 v s = 2.5v r l = 100 standby (1,0) or (0,1) (1,1) full power 1,%(" %7!
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rev. a ad8018 C6C 500 500 500 500 25 ad8138 50 500 750 750 6v 6v v s v s 10 f0.1 f 220 f 0.1 f r l vsig in 6v 0.1 f 6v 0.1 f 7.96k 7.96k 402 402 50 out 100 100 ad8018 1/2 ad8018 1/2 ad9632 0.1 f 10 f0.1 f tpc 13. differential test circuit frequency mhz differential distortion dbc 110 0.01 0.1 100 90 80 70 60 1.0 3rd harmonic 2nd harmonic v out = 6v p p r l = 10 v s = 2.5v pwdn 1,0 = 1,1 tpc 14. differential distortion vs. frequency peak output current ma differential distortion dbc 110 200 2nd harmonic 300 400 500 600 700 800 100 90 80 70 60 50 3rd harmonic v s = 2.5v r l = 3 g = 4 f o = 100khz pwdn 1,0 = 1,1 tpc 15. differential distortion vs. peak output current load resistance differential distortion dbc 110 510 100 100 90 80 70 60 3rd harmonic 2nd harmonic v s = 2.5v g = 4 f o = 100khz v out = 6v p p tpc 16. differential distortion vs. r load output voltage volts differential distortion dbc 110 3 45 678 100 90 80 70 60 3rd harmonic 2nd harmonic v s = 2.5v r l = 10 g = 4 f o = 100khz pwdn 1,0 = 1,1 tpc 17. differential distortion vs. peak-to-peak output voltage output voltage volts differential distortion dbc 110 3 3rd harmonic 45678 100 90 80 70 60 2nd harmonic v s = 2.5v r l = 10 g = 4 f o = 100khz pwdn 1,0 = 1,0 or 0,1 tpc 18. differential distortion vs. peak-to-peak output voltage
rev. a ad8018 C7C transformer turns ratio p line dbm 3.0 16 10 11 12 13 14 15 3.2 4.0 4.2 4.4 4.6 4.8 3.4 3.6 3.8 v s = 5.25 v s = 4.75 v s = 5.00 tpc 19. line power vs. turns ratio; mtpr = C65 dbc, f = 43 khz transformer turns ratio n mtpr dbc 3 4 80 70 60 50 40 30 5 20 p = 13dbm p = 13.5dbm p = 14dbm p = 12.5dbm p = 12dbm v s = 5v r line = 100 f = 93khz tpc 20. mtpr vs. turns ratio transformer turns ratio n sfdr dbc 3 90 4 80 70 60 50 40 30 5 p = 12dbm p = 12.5dbm p = 13dbm p = 13.5dbm p = 14dbm v s = 5v r line = 100 f = 361khz tpc 21. out-of-band sfdr vs. turns ratio for various line power transformer turns ratio p line dbm 3.0 16 6 8 10 14 3.2 4.0 4.2 4.4 4.6 3.4 3.6 3.8 18 12 v s = 4.75 v s = 8.00 v s = 5.00 v s = 3.3 v s = 4.50 4.8 1,%"" ',
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-5;/ *) $ $ * #!.69(23 frequency hz 1k 10k 100k 1m 10m 100m 1g 0.01 0.1 1 10 100 1k 10k 100k 1m 10m transimpedance 150 100 50 0 50 200 100 150 phase de g rees transimpedance phase 200 tpc 23. open loop transimpedance and phase power-down voltage volts total supply current ma 0.86 16 6 8 10 14 decreasing 18 12 20 0.88 0.90 0.92 0.94 0.96 0.98 1.00 1.02 increasing logic 1 to 0 logic 0 to 1 tpc 24. power-up/-down threshold voltage
rev. a ad8018 C8C theory of operation the ad8018 is composed of two current feedback amplifiers capable of delivering 400 ma of output current while swinging to within 0.5 v of either power supply, and maintaining low distortion. a differential line driver using the ad8018 can provide cpe performance on a single 5 v supply. this performance is enabled by analog devices xfcb process and a novel, two- stage current feedback architecture featuring a patent-pending rail-to-rail output stage. a simplified schematic is shown in figure 4. emit ter followers buffer the positive input, v p , to provide low input current and current noise. the low impedance current feedback summing junction is at the negative input, v n . the output stage is another high-gain amplifier used as an integrator to provide frequency compensation. the complementary common-emitter output provides the extended output swing. a current feedback amplifiers dynamic and distortion perform ance is relatively insensitive to its closed-loop signal gain, which is a distinct advantage over a voltage-feedback architecture. figure 5 shows a simplified model of a current feedback amplifier. the feedback signal is a current into the inverting node. r in is inversely proportional to the transconductance of the amplifiers input stage, g mi . circuit analysis of the pictured follower with gain yields: vv g t trgr out in zs zs f in / () () = ++ where: grr t r cr rg fg zs t s tt in mi =+ = + =? 1 1 1 125 / () / () ? recognizing that g r in < r f , and that the C 3 db point is set when t z(s) = r f , one can see that the amplifier s bandwidth depends primarily on the feedback resistor. there is a value of r f below which the amplifier will be unstable, as an actual ampli- fier will have additional poles that will contribute excess phase shift. the optimum value for r f depends on the gain and the amount of peaking tolerable in the application. v o bias v n v p figure 4. simplified schematic g = 1 i t = i in c t r t i in v out r g r f r in + v in v o + figure 5. model of current feedback amplifier feedback resistor selection in current feedback amplifiers, selection of the feedback and gain resistors will impact the mtpr performance, bandwidth, n oise, and gain flatness. care should be exercised in the selection of these resistors so that the optimum performance is achieved. table i shows the recommended resistor values for use in a variety of gain settings for the test circuit in tpc 1. these values are intended to be a starting point when designing for any application. frequency hz crosstalk db 90 1m 10m 100m 1g 80 70 60 50 40 30 20 10 r l = 5 side a driven r l = 5 side b driven v in = 2v p-p g = 2 v s = 2.5 100k r l = 100 side a driven r l = 100 side b driven 100 110 tpc 25. crosstalk vs. frequency
rev. a ad8018 C9C table i. resistor selection guide gain r f ( )r g ( ) C 1 681 681 +1 1 k +2 750 750 +3 511 256 +4 340 113 +5 230 59 power-down features two digitally programmable logic pins, pwdn1 and pwdn0, are available on the tssop-14 package to select among three different modes of operation, full power, standby and shutdown. the dgnd pin is the logic ground reference. the logic thresh- old voltage is established 1 v above dgnd. in a typical 5 v single-supply application, the dgnd pin is connected to analog ground. if pwdn1, pwdn0, and dgnd are left unconnected, the ad8018 will operate at full power. table ii. power-down features and truth table supply output pwdn0 pwdn1 state current impedance high high full power 18 ma low low high standby 9 ma low high low standby 9 ma low low low disabled 300 a high power supply and decoupling the ad8018 can be powered with a good quality (i.e., low-noise) supply anywhere in the range from 3.3 v to 8 v. however, in order to optimize the adsl upstream drive capability to +13 dbm and m aintain the best spurious free dynamic r ange (sfdr), the ad8018 circuit should be supplied with a well regulated 5 v supply. the 5 v supplied at the universal serial bus (usb) port may be poorly regulated. improving the qu ality of the 5 v supply will optimize the performance of the ad8018 in a universal serial bus-supplied cpe adsl modem. this can be accomplished through the use of a step-up dc-to-dc converter or sw itching power supply followed by a low dropout (ldo) regulator such as the adp3331 (see figure 6). setting r1 to be 953 k ? and r2 to be 301 k ? will result in a v out of 5 v. careful attention must be paid to decoupling the power supply pins at the output of the dc-to-dc converter, the output of the ldo regulator and the supply pins of the ad8018. high-quality capacitors with low equivalent series resistance (esr) such as multilayer ceramic capacitors (mlccs) should be used to m ini- mize supply voltage ripple and power dissipation. a large, usually tantalum, 10 f to 47 f capacitor located in proximity to the ad8018 is required to provide good decoupling for lower fre- quency signals. in addition, 0.1 f mlcc decoupling capacitors should be located as close to each of the power supply pins as is physically possible, no more than 1/8 inch away. an addit ional large (4.7 f to 10 f) tantalum capacitor should be placed on the board near the supply terminals to supply current for fast, large- signal changes at the ad8018 outputs. adp3331 c1 0.47 f v in on off v out e out c2 0.47 f r3 330k in sd gnd out fb err r1 953k r2 301k figure 6. adp3331 ldo method for generating a midsupply voltage to operate an amplifier on a single voltage supply, a voltage midway between the supply and ground must be generated to properly bias the inputs and the outputs. a voltage divider can be created with two equal value resistors (figure 7). there is a trade-off between the power consumed by the divider and the voltage drop across these resistors due to the positive input bias currents. selecting 2.5 k ? for r1 and r2 will create a voltage divider that draws only 1 ma from a 5 v su pply. the voltage generated with this topology can vary due to the temperature coefficient (tc) of resistance. resistors that are closely matched and have a low tc will minimize variations in the voltage reference due to temperature. one should also be sure to use a decoupling capacitor (0.1 f) at the node where v ref is generated. 5v r1 2.5k r2 2.5k v ref 0.1 f figure 7. midsupply reference differential testing the test circuit shown in tpc 13 is used for measuring the dif- ferential distortion of the ad8018. a single-ended test signal is applied to the inverting input of the ad8138 differential driver with the noninverting input grounded. applying the differential output of the ad8138 through 100 ? resistors serves to isolate the inputs of the ad8018 differential driver and provide a well- balanced low-distortion input signal. the differential load (r l ) of the ad8018 can be set to the equivalent of the line imped- ance reflected t hrough a transformer. the ad9632 converts the differential output voltage back to a single-ended signal. the differential-to- single-ended converter using the ad9632 has an attenuation of C 26 db and is wired with precision resis- tors to optimize the balance of differential input signal. the resulting smaller output signal can be easily measured using a 50 ? spectrum analyzer.
rev. a ad8018 C10C p v rmsv v rms r iv p tot o s o l q s out =++ 408 1 2 2 (. C ) for the ad8018, operating on a single 5 v supply and deliver- ing a total of 16 dbm (13 dbm to the line and 3 dbm to the matching network) into 12.5 ? (100 ? reflected back through a 1:4.0 transformer plus back termination), the power is: = 261 mw + 40 mw = 301 mw using these calculations, and a ja of 115 c/w for the tssop package and 100 c/w for the soic, tables iii and iv show junction temperature versus power delivered to the line for sev- eral supply voltages. table iii. junction temperature vs. line power and operating voltage for tssop, t amb = 85 c v supply p line, dbm 5 6 7 8 13 115 122 129 136 14 117 125 132 140 15 119 127 136 144 16 121 130 139 148 17 123 133 143 153 18 125 136 147 158 table iv. junction temperature vs. line power and operating voltage for soic, t amb = 85 c v supply p line, dbm 5 6 7 8 13 111 117 123 129 14 113 119 126 133 15 115 122 129 136 16 116 124 132 140 17 118 127 136 144 18 120 130 139 149 running the ad8018 at voltages near 8 v can produce junction temperatures that exceed the thermal rating of the tssop pack- ages and should be avoided. the shaded areas indicate junction temperatures greater than 150 c. layout considerations as is the case with all high-speed applications, careful attention to printed circuit board layout details will prevent associated board parasitics from becoming problematic. proper rf design technique is mandatory. the pcb should have a ground plane covering all unused portions of the component side of the board to provide a low-impedance return path. removing the ground plane on all layers from the area near the input and output pins will reduce stray capacitance, particularly in the area of the inverting inputs. signal lines connecting the feedback and gain resistors should be as short as possible to minimize the inductance and stray capacitance associated with these traces. termination resistors and loads should be located as close as possible to their respective inputs and outputs. input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) though the board. adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended. this circuit requires significant power supply bypassing. the ad8018 operates on a split supply in this circuit. the bypassing technique shown in tpc 13 utilizes a 220 f tantalum ca pacitor and a 0.1 f ceramic chip capacitor in parallel, connected from the positive to negative supply, and a 10 f tantalum and 0.1 f ceramic chip capacitor in parallel, connected from each supply to ground. the capacitors connected between the power supplies serve to minimize any voltage ripples that might appear at the supplies while sourcing or sinking any large differential current. the large capacitor has a pool of charge instantly available for the ad8018 to draw from, thus preventing any erroneous dis- tortion results. power dissipation it is important to consider the total power dissipation of the ad8018 in order to properly size the heat sink area of an application. f igure 8 is a simple representation of a differential driver. with some simplifying assumptions we can estimate the total power dissipated in this circuit. if the output current is large com pared to the quiescent current, computing the dissipa- tion in the output devices and adding it to the quiescent p ower dissipation will give a close approximation of the total power dissipation in the package. a factor (~0.6-1) corrects for the slight error due to the class a/b operation of the output stage. it can be estimated by subtracting the quiescent current in the output stage from the total quiescent current and ratioing that to the total quiescent current. for the ad8018, = 0.833. +v s v s +v o +v s v s v o r l figure 8. simplified differential driver remembering that each output device dissipates for only half the time gives a simple integral that computes the power for each device: 1 2 2 ? ? ? ? ? ? ( C ) vv v r so o l the total supply power can then be computed as: pvvv r iv p tot s o o l q s out = ? ? ? ? ? + + 4 1 2 2 || in this differential driver, v o is the voltage at the output of one amplifier, so 2 v o is the voltage across r l , which is the total impedance seen by the differential driver, including back termina- tion. now, with two observations, the integrals are easily evaluated. first, the integral of v o 2 is simply the square of the rms value of v o . second, the integral of |v o | is equal to the a verage recti- fied value of v o , sometimes called the mean average d eviation, or mad. it can be shown that for a discrete multitone (dmt) signal, the mad value is equal to 0.8 times the rms value.
rev. a ad8018 C11C following these generic guidelines will improve the performance of the ad8018 in all applications. to optimize the ad8018 s performance as an adsl differential line driver, locate the transformer hybrid near the ad8018 drivers and as close to the rj11 jack as possible. maintain differential circuit symmetry into the differential driver and from the output of the drivers through the transformer-coupled output of the bridge circuit as much as possible. cpe adsl application the low-cost, high-output current dual ad8018 xdsl driver amplifiers have been specifically designed to drive high fidelity xdsl signals to within 0.5 v of the power rails, the performance needed to provide cpe adsl on a single 5 v supply. the ad8018 may be used in transformer-coupled bridge hybrid cir- cuits to drive modulated signals including discrete multitone (dmt) upstream to the central office. evaluation board the ad8018aru-eval evaluation board circuit in figure 12 offers the ability to evaluate the ad8018 in a typical xdsl bridge hybrid circuit. the receiver circuit on these boards is typically unpopulated. requesting samples of the ad8022ar with the ad8018aru- eval board will provide the capability to evaluate the ad8018aru along with other analog devices products in a typi- cal transceiver circuit. the evaluation circuits have been designed to replicate the cpe side analog transceiver hybrid circuits. the circuit mentioned above is designed using a one -transformer transceiver topology including a line receiver, line driver, line matching network, an rj11 jack for interfacing to line simulators, and transformer-coupled inputs for single-ended-to-differential input conversion. ac-coupling capacitors of 0.01 f, c8, and c10, in combina- tion with 10 k ? resistors r24 and r25, will form a zero frequency at 1.6 khz. transformer selection customer prem ise adsl requires the transmis sion of a +13 dbm (20 mw) dmt signal. the dmt signal can have a crest factor as high as 5.3, requiring the line driver to provide peak line power of 27.5 dbm (560 mw). 27.5 dbm peak line power translates into a 7.5 v peak voltage on the 100 ? telephone line. assuming that the maximum low-distortion output swing available from the ad8018 line driver on a 5 v supply is 4 v and, taking into account the power lost due to the termination resistance, a step-up trans former w ith turns ratio of 4.0 or greater is needed. in the simplified differential drive circuit shown in figure 2, the ad8018 is coupled to the phone line through a step-up trans- former with a 1:4 turns ratio. r1 and r2 are back-termination or line-matching resistors, each 3.1 ? (100 ? /(2 4 2 )), where 100 ? is the approximate phone line impedance. the total dif- ferential l oad for the ad8018, including the termination resistors, is 12.5 ? . even under these conditions the ad8018 provides low distortion signals to within 0.5 v of the power rails. stability enhancements the cpe bridge hybrid circuit presents a complex impedance to the drive amplifiers, particularly when transformer parasitics are factored in. to ensure stable operation under the full range of load conditions, a series r-c network (zoebel network) should be connected between each amplifier s output and ground. the recommended values are 10 ? for the resistor and 1 nf for the capacitor to create a low impedance path to ground at frequen- cies above 16 mhz (see figure 2). r33 and r34 are added to improve common-mode stability. receive channel considerations a transformer used at the output of the differential line driver to step up the differential output voltage to the line has the inverse effect on signals received from the line. a voltage reduction or attenuation equal to the inverse of the turns ratio is realized in the receive channel of a typical bridge hybrid. the turns ratio of the transformer may also be dictated by the ability of the re ceive circuitry to resolve low-level signals in the noisy twisted pair tele- phone plant. higher turns ratio transformers effectively reduce the received signal-to-noise ratio due to the reduction in the received signal strength. the ad8022, a dual amplifier with typical rti voltage noise of only 2.5 nv/ hz and a low supply current of 4 ma/amplifier, is recommended for the receive channel. dmt modulation, multitone power ratio (mtpr), and out-of-band sfdr adsl systems rely on dmt modulation to carry digital data over phone lines. dmt modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which is uniformly separated in frequency. a uniquely encoded, q uadra- ture amplitude modulation (qam)-like signal occurs at the center frequency of each subband or tone. see figure 9 for an example of a dmt waveform in the frequency domain, and figure 10 for a time domain waveform. difficulties will exist when decoding these subbands if a qam signal from one subband is corrupted by the qam signal(s) from other subbands, regardless of w hether the corruption comes from an adjacent subband or harmonics of other subbands. conventional methods of expressing the output signal integrity of line drivers, such as single-tone harmonic distortion or thd, two-tone intermodulation distortion (imd), and third order intercept (ip3), become significantly less meaningful when amplifiers are required to process dmt and other heavily modulated waveforms. a typical adsl upstream dmt signal can contain as many as 27 carriers (subbands or tones) of qam signals. m ultitone power ratio (mtpr) is the relative difference betw een the measured power in a typical subband (at one tone or carrier) versus the power at another subband spe- cifically selected to contain no qam data. in other words, a selected subband (or tone) r emains open or void of intentional power (without a qam signal), yielding an empty frequency bin. mtpr, sometimes referred to as the empty bin test, is typically expressed in dbc, similar to expressing the relative difference between single-tone fundamentals and second or third harmonic distortion components. measurements of mtpr are typically made on the line side or secondary side of the transformer.
rev. a ad8018 C12C frequency khz 20 80 0 150 50 power dbm 100 60 40 20 0 figure 9. dmt waveform in the frequency domain mtpr versus transformer turns ratio is depicted in tpc 21 and covers a variety of line power ranging from +12 dbm to +14 dbm. as the turns ratio increases, the driver hybrid can deliver more undistorted power due to higher output current capability. significant degradation of mtpr will occur if the output of the driver swings to the rails, causing clipping at the dmt voltage peaks. driving dmt signals to such extremes not only compro- mises in-band mtpr, but will also produce spurs that exist outside of the frequency spectrum containing the desired dmt power. out-of-band spurious free dynamic range (sfdr) can be defined as the relative difference in amplitude between these spurs and a tone in one of the upstream bins. compromising out-of-band sfdr is equivalent to increasing near end cross- talk (next). regardless of terminology, maintaining out-of-band sfdr while reducing next will improve the overall performance of the modems connected at either end of the twisted pair. tpc 21 shows how sfdr varies versus transformer turns ratio for line power ranging from +12 dbm to +14 dbm. as line power increases, or turns ratio decreases, sfdr degrades. the power contained in the spurs can be measured relative to the power contained in a typical upstream carrier and is expressed in dbc as sfdr, similar to mtpr. the supply voltage of the driver can also affect sfdr. as the supply voltage is increased, voltage swing is increased as well, resulting in the ability to deliver more power to the line with- out sacrificing performance. this can be seen in tpc 22. less undistorted power is available when lower turns ratio transform- ers are used due to voltage clipping of the signal. txdac is a trademark of analog devices, inc. time ms 4 0.25 volts 0 3 1 0 2 0.2 1.5 1.0 0.05 0.05 1.0 1.5 0.2 3 2 1 figure 10. dmt signal in the time domain generating dmt signals at this time, dmt-modulated waveforms are not typically menu-selectable items contained within awgs. even using awg software to generate dmt signals, awgs that are available today may not deliver dmt signals suffic ient in performance with regard to mtpr due to limitations in the d/a converters and output drivers used by awg manufacturers. similar to evaluating single-tone distortion performance of an amplifier, mtpr evaluation requires a dmt signal generator capable of delivering mtpr performance better than that of the driver under evaluation. generating dmt signals can be accom- plished using a tektronics awg 2021 equipped with option 4, (12-/24-bit, ttl digital data out), digitally coupled to analog devices ad9754, a 14-bit txdac ? , buffered by an ad8002 amplifier configured as a differential driver. note that the dmt waveforms (available on the analog devices website, http://www.analog.com), or similar .wfm files are needed to produce the digital data required to drive the txdac from the optional ttl digital data output of the tek awg2021.
rev. a ad8018 C13C u1 ad8018 +v r18 750 tp6 r8 100 r3 10 r19 750 r4 10 c22 1000pf c27 1000pf u1 ad8018 +v tp8 r21 dni c12 dni tp9 pr2 r1 10 1watt r2 750 v cc -t u2 ad8022 dni r6 dni tp17 r7 dni vcc-r agnd;4 v cc ;8 agnd;4 tp18 r13 dni c16 dni c3 dni tp5 r12 dni c1 dni c2 dni tp4 r9 dni r10 dni c5 0.1 f r29 10k r24 10k c8 0.1 f tp10 c10 0.1 f r14 100 tp11 c28 dni r30 0 v cc r11 50 r15 50 v cc p4 2 p4 1 p4 3 55 53 p3 2 p3 3 p3 1 54 56 r5 dni v cc r17 2.49k jp4 a b 3 2 jp3 1 1 2 3 b a c4 dni cappoly c7 dni cappoly nc = 5,6 t1 3 2 1 4 8 9 7 10 1 2 3 4 5 6 tp1 78 tp2 c9 dni cappoly cappoly c6 dni tb1 1 c18 dni v cc -t tp19 c17 10 f 25v c15 0.01 f c26 0.1 f c14 10 f l5 bead 2 tb1 c19 dni 25v c23 dni u2 decoupling tp23 tp24 tp25 tp26 r32 dni 1 2 r20 dni c11 dni tp7 pr1 r31 0 v cc -r v cc -r dni: do not install v cc 2 v cc 2 v cc -t r33 10k r34 10k r16 2.49k c20 0.1 f u2 ad8022 dni v cc 2 figure 11. eval board schematic jp1 nc1 nc2 nc3 pdn0 pdn1 dgnd u1 ad8018 0.1 f c25 0.1 f c24 100 r25 100 r26 r28 dni r27 dni v cc jp2 figure 12. input control circuit
rev. a ad8018 C14C figure 13. assemblyprimary side figure 14. silk screenprimary side
rev. a ad8018 C15C figure 15. layer 1primary side figure 16. layer 2ground plane
rev. a ad8018 C16C figure 17. layer 3power plane figure 18. layer 4secondary side
rev. a ad8018 C17C figure 19. assemblysecondary side
rev. a ad8018 C18C evaluation board?ill of materials qty. description vendor ref desc. 2 1,000 pf 50 v. 1206 ceramic chip capacitor ads # 4-5-20 c22, 27 2 0.01 f 50 v. 1206 ceramic chip capacitor ads # 4-5-19 c15, 23 5 0.1 f 50 v. 1206 size ceramic chip capacitor ads # 4-5-18 c5, 20, 24 -26 2 1.0 f 16 v. 1206 size ceramic chip capacitor newark # 83f6841 c8, 10 4 # 26 red (solid) wire jumper ads # 10-14-3 c4, 6, 7, 9 3 10 f 16 v. c size tantalum chip capacitor ads # 4-7-6 c14, 17, 19 1 ferrite bead (with # 22 wire) ads # 48-1-1 l5 1 10 ? 5% 3.0 w. metal oxide power resistor d-k # p10w-3bk-nd r1 60 ? 5% 1/8 w. 1206 size chip resistor ads # 3-18-88 c11, 12, r20, 21, 30, 31 2 10.0 ? 1% 1/8 w. 1206 size chip resistor ads # 3-18-120 r3, 4 2 49.9 ? 1% 1/8 w. 1206 size chip resistor ads # 3-14-26 r11, 15 5 100 ? 1% 1/8 w. 1206 size chip resistor ads # 3-18-40 r8, 14, 25, 26, 32 2 2.49 k ? 1% 1/8 w. 1206 size chip resistor ads # 3-18-71 r16, 17 3 750 ? 1% 1/8 w. 1206 size chip resistor ads # 3-18-8 r2, 18, 19 2 10.0 k ? 0.1% 0805 size chip resistor ads # 3-36-5 r33, 34 2 10.0 k ? 1% 1/8 w. 1206 size chip resistor ads # 3-18-119 r24 and 29 4 test point (black) [gnd] ads # 12-18-44 tp23 C 26 (gnd.) 2 test point (brown) ads # 12-18-59 tp4, 5 3 test point (red) ads # 12-18-43 tp17 C 19 4 test point (orange) ads # 12-18-60 tp1, 2, 10, 11 1 test point (yellow) ads # 12-18-32 tp3 2 test point (blue) ads # 12-18-62 tp6, 8 2 test point (green) ads # 12-18-61 tp7, 9 12 5-pin strips (1/4 of a 20-pin samtek sip strip socket) ads # 11-2-14 (t1) 1 2 pos. gray term. blk. # 25.161.0253 (newark # 51f4106) ads# 12-19-10 tb1, 2 4 0.1 inch ctr. shunt berg # 65474 -001 ads # 11-2-38 jp1 C 4 2 2 pin gold male header 0.1 inch ctr. berg # 69157 -102 ads # 11-2-37 jp1, 2 4 50 ? bnc pc mount telegartner # j01001a1944 ads # 12-6-22 s3 C 6 1 amp# 555154 -1 mod. jack (shielded) 6 C 6 ads # 12-20-5 p1 2 3-pin gold male header waldom d-k # wm 2723 -nd ads # 12-3-80 jp3, 4 2 3-pin gold male locking header waldom # wm 2701 -nd ads # 12-3-79 p3, 4 1 ad8018aru adsl driver hybrid ads # ad8018aru u1 (d.u.t.) 1 ad8018 tssop1t non-inverting rev. a evaluation pc board d c s eval. pc board 4# 4 C 40 1/4" panhead ss machine screw ads # 30-1-1 4# 4 C 40 1/2" threaded alum. standoffs ads # 30-16-2
rev. a ad8018 C19C outline dimensions dimensions shown in inches and (mm). 8 lead soic (so-8) 0.0098 (0.25) 0.0075 (0.19) 0.050 (1.27) 0.016 (0.40) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 85 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.020 (0.51) 0.013 (0.33) controlling dimensions are in millimeters all dimensions per jedec standards ms-012 aa 14 lead tssop (ru-14) 0.177 (4.50) 0.173 (4.40) 0.169 (4.30) 14 8 7 1 0.252 (6.40) bsc pin 1 0.201 (5.10) 0.197 (5.00) 0.193 (4.90) 0.0256 (0.65) bsc seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.047 (1.2) max 0.059 (1.50) 0.093 (1.00) 0.031 (0.80) 0.008 (0.20) 0.004 (0.09) 8 0 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) controlling dimensions are in millimeters c01519aC.5C11/00 (rev. a) printed in u.s.a.

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